Generally, in the fabrication of an IC device, photolithographic processes may be utilized to print/pattern cavities, trenches, and/or recessed-areas for creating various devices, elements, and circuits. Different types of cavities may be formed at different stages of the fabrication process. For instance, the cavities may have different shapes, depths and/or sizes and may be created in different regions of a substrate. For example, a cavity intended to form a contact may have one size and aspect ratio (e.g., depth to width ratio), may be at a certain location in the substrate, and may be filled with a particular material such as tungsten (W), whereas trenches for metal lines may have a different size and aspect ratio and may be filled with a different material such as copper (Cu). The metal line trenches or channels in a metal layer may be filled with Cu for interconnecting different devices in the IC whereas a shallow trench isolation (STI) region may be filled with an oxide for electrically isolating various devices from each other. In the semiconductor industry, advanced technologies are used to design and manufacture smaller IC devices that may include circuit elements (e.g., transistor, interconnecting wires, vias, etc.) with smaller geometries. However, in smaller IC devices, the cavities that are to be filled with different materials may also shrink, which may present various challenges. For example, a trench filled with a material (e.g., Cu) may be filled such that void spots/areas may develop, which may be due insufficient/irregular filling of the material. The voids may degrade interconnectivities between various layers or elements in the IC device and cause performance or reliability issues. The voids may, for instance, be due to a high aspect ratio of a trench (e.g., too deep) where the filling material may not fully fill the trench.
FIG. 1A is a cross sectional diagram of various layers in an example IC device. FIG. 1A illustrates stack 100 including an interlayer dielectric (ILD) 101 over a silicon (Si) substrate (not shown for illustrative convenience), active area and gate contacts (e.g., W) 103a through 103d, an etch stop layer 105, another ILD 107, a dielectric hard-mask (DHM) layer 109 (such as silicon oxynitride (SiON)), a metal hard-mask (MHM) layer 111 (e.g., titanium nitride (TiN)), and a metal (e.g., Cu) layer 113 formed on upper surface of the MHM layer 111. Additionally, the metal layer may fill cavities/trenches 115 and 117 (e.g., via or metal line trenches) that may have been formed by various IC manufacturing (e.g., litho-etch) processes. A thin barrier/seed layer 119 may be formed in the cavities, prior to filling with metal.
FIGS. 1B and 1C illustrate cross-sectional views of structures in an example IC device. In FIG. 1B, image 121 includes a trench 115, which is filled with a material (e.g., Cu); however, there is a void 123 that may be due to insufficient filling material. Also, FIG. 1C depicts image 125 that illustrates a different view of the void 123.
As illustrated, different cavities/trenches (e.g., 115 or 117) may be at different depths yielding different aspect ratios. In instances of a deep trench (e.g., high aspect ratio), it is possible that the trench may not be completely filled with an intended material, wherein voids or gaps may exist. As noted, such voids or gaps may contribute to performance or reliability issues in an IC device.
A need therefore exists for a methodology enabling filling of high aspect ratio cavities, with no voids or gaps, in an IC device and the resulting device.